This disclosure relates to electrical circuits and signal processing.
Disk drive systems traditionally employ a phase locked loop (PLL) for retrieval of data from a data signal encoded onto a magnetic medium (e.g., a floppy diskette). The PLL allows a signal frequency to be precisely controlled and, accordingly, permits the data encoded onto a magnetic medium to be reliably decoded at a stable, known frequency.
A conventional PLL frequency synthesizer is shown in FIG. 1 and includes a voltage controlled oscillator (VCO) 100 that produces a VCO output signal 102 at a desired frequency based on a VCO frequency control signal 104. VCO frequency control signal 104 is generated by a feedback loop 106. VCO output signal 102 is coupled through feedback loop 106 to a phase frequency detector 108 which compares the phase (or frequency) of VCO output signal 102 (or multiple thereof as described below) to that of a fixed frequency reference signal 110. Phase frequency detector 108 generates an error signal 112 corresponding to a phase (or frequency) difference between VCO output signal 102 and fixed frequency reference signal 110. A charge pump 114 converts error signal 112 from phase frequency detector 108 into a charge pump output signal 116. Charge pump output signal 116 is smoothed by a low pass loop filter 118 to generate VCO control signal 104. VCO control signal 104 is then applied to VCO 100 such that the phase (or frequency) of VCO output signal 102 matches that of fixed frequency reference signal 110.
Typically, a frequency divider 120 is included in PLL feedback loop 106 to divide the frequency of VCO output signal 102 to a frequency that is a multiple of that of fixed frequency reference signal 110. Frequency divider 120 generates a divided frequency output signal 122 that is compared by phase frequency detector 108 to fixed frequency reference signal 110. The frequency of a signal produced by VCO 100 is constantly controlled such that it is phase locked to a multiple of that of fixed frequency reference signal 110. For example, if frequency divider 120 divides by integers only, the smallest increment (i.e., step size) in the frequency of VCO output signal 102 is equal to the frequency of fixed frequency reference signal 110.
To increase the VCO output frequency resolution, frequency divider 120 is typically implemented as a fractional divider. A fractional divider fractionally divides an input signal. However, a conventional PLL including a fractional divider may introduce undesirable phase jitter or phase noise in VCO output signal 102.
A frequency multiplier 124 can also be included within feedback loop 106 to increase the VCO output frequency resolution. Frequency multiplier 124 is typically implemented using a second PLL that may introduce additional phase jitter or phase noise.